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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Low Voltage 1:15 Differential
/1//2
ECL/PECL Clock Driver
MC100LVE222
The MC100LVE222 is a low voltage, low skew 1:15 differential /1//2 ECL fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The LVE222 can be used as a simple fanout buffer or outputs can be configured to provide half frequency outputs. The combination of 1x and 1/2x frequencies is flexible providing for a myriad of combinations. All timing differences between the 1x and 1/2x signals are compensated for internal to the chip so that the output-to-output skew is identical regardless of what output frequencies are selected.
LOW VOLTAGE 1:15 DIFFERENTIAL /1//2 ECL/PECL CLOCK DRIVER
* * * * * * *
Fifteen Differential Outputs 200ps Part-to-Part Skew 50ps Output-to-Output Skew Selectable 1x or 1/2x Frequency Outputs Extended Power Supply Range of -3.0V to -5.25V (+3.0V to +5.25V) 52-Lead TQFP Packaging ESD > 2000V
FA SUFFIX The fsel and CLK_Sel input pins are asynchronous control signals. As TQFP PACKAGE a result, changing these inputs could cause indeterminent excursions on CASE 848D-03 the outputs immediately following the changes on the inputs. For applications which require a single-ended input, the VBB reference voltage is supplied. For single-ended input applications the VBB reference should be connected to the CLK input and bypassed to ground via a 0.01f capacitor. The input signal is then driven into the CLK input. To ensure that the tight skew specification is met it is necessary that both sides of the differential output are terminated into 50, even if only one side is being used. In most applications all fifteen differential pairs will be used and therefore terminated. In the case where fewer than fifteen pairs are used it is necessary to terminate at least the output pairs adjacent to the output pair being used in order to maintain minimum skew. Failure to follow this guideline will result in small degradations of propagation delay (on the order of 10-20ps) of the outputs being used, while not catastrophic to most designs this will result in an increase in skew. Note that the package corners isolate outputs from one another such that the guideline expressed above holds only for outputs on the same side of the package. The MC100LVE222, as with most ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVE222 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE222's performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage of VCC-2.0V will need to be provided. For more information on using PECL, designers should refer to Motorola Application Note AN1406/D. The MC100LVE222 is packaged in the 52-lead TQFP package. For a 3.3V supply this package provides the optimum performance and minimizes board space requirements. The LVE222 will operate from a standard 100E -4.5V supply or a 5.0V PECL supply. The 52-lead TQFP utilizes a 10x10mm body with a lead pitch of 0.65mm.
10/96
(c) Motorola, Inc. 1996
4-1
REV 1
MC100LVE222
Pinout: 52-Lead TQFP (Top View)
VCCO VCCO VCCO 27 26 25 24 23 22 21 Qd0 Qd0 Qd1 Qd1 Qd2 Qd2 Qd3 Qd3 Qd4 Qd4 Qd5 Qd5 VCCO 20 19 18 17 16 15 14 1 2 3 4 5 6 7 8 9 10 11 12 13 Qc0 Qc0 Qc1 Qc1 Qc2 Qc2 Qc3 Qc3 NC 29 NC 28 fseld
39 VCCO Qb2 Qb2 Qb1 Qb1 Qb0 Qb0 VCCO Qa1 Qa1 Qa0 Qa0 VCCO 40 41 42 43 44 45 46 47 48 49 50 51 52
38
37
36
35
34
33
32
31
30
MC100LVE222
CLK_Sel
CLK0
CLK0
CLK1
CLK1
VCC
MR
VBB
fsela
fselb
LOGIC SYMBOL
MR CLK0 CLK0 CLK1 CLK1 CLK_Sel VBB fsela 3 Qb0:2 Qb0:2 /1 /2 2
Qa0:1 Qa0:1
fselc
FUNCTION TABLE
Function Input MR CLK_Sel fseln 0 Active CLK0 /1 1 Reset CLK1 /2
fselb 4 Qc0:3 Qc0:3
fselc 6 Qd0:5 Qd0:5
fseld
MOTOROLA
4-2
VEE
ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC100LVE222
ECL DC CHARACTERISTICS
-40C Symbol VOH VOL VIH VIL VBB VEE IIH IIL IEE Characteristic Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output Reference Voltage Power Supply Voltage Input HIGH Current Input CLK0, CLK1 LOW Current Others Power Supply Current -300 0.5 122 136 Min -1.085 -1.830 -1.165 -1.810 -1.38 -3.0 Typ -1.005 -1.695 Max -0.880 -1.555 -0.880 -1.475 -1.26 -5.25 150 -300 0.5 122 136 Min -1.025 -1.810 -1.165 -1.810 -1.38 -3.0 0C Typ -0.955 -1.705 Max -0.880 -1.620 -0.880 -1.475 -1.26 -5.25 150 -300 0.5 122 136 Min -1.025 -1.810 -1.165 -1.810 -1.38 -3.0 25C Typ -0.955 -1.705 Max -0.880 -1.620 -0.880 -1.475 -1.26 -5.25 150 -300 0.5 125 139 Min -1.025 -1.810 -1.165 -1.810 -1.38 -3.0 70C Typ -0.955 -1.705 Max -0.880 -1.620 -0.880 -1.475 -1.26 -5.25 150 Unit V V V V V V A A mA
PECL DC CHARACTERISTICS
-40C Symbol VOH VOL VIH VIL VBB VCC IIH IIL IEE Characteristic Output HIGH Voltage1. Min 2.215 1.470 2.135 1.490 1.92 3.0 Typ 2.295 1.605 Max 2.420 1.745 2.420 1.825 2.04 5.25 150 -300 0.5 122 136 -300 0.5 122 136 Min 2.275 1.490 2.135 1.490 1.92 3.0 0C Typ 2.345 1.595 Max 2.420 1.680 2.420 1.825 2.04 5.25 150 -300 0.5 122 136 Min 2.275 1.490 2.135 1.490 1.92 3.0 25C Typ 2.345 1.595 Max 2.420 1.680 2.420 1.825 2.04 5.25 150 -300 0.5 125 139 Min 2.275 1.490 2.135 1.490 1.92 3.0 70C Typ 2.345 1.595 Max 2.420 1.680 2.420 1.825 2.04 5.25 150 Unit V V V V V V A A mA
Output LOW Voltage1. Input HIGH Input LOW Voltage1. Voltage1.
Output Reference Voltage1. Power Supply Voltage Input HIGH Current Input CLK0, CLK1 LOW Current Others Power Supply Current
1. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
ECLinPS and ECLinPS Lite DL140 -- Rev 3
4-3
MOTOROLA
MC100LVE222
ECL AC CHARACTERISTICS (VEE = VEE (min) to VEE (max); VCC = VCCO = GND)
-40C Symbol tPLH tPHL Characteristic Propagation Delay to Output IN (differential) IN (single-ended) MR Within-Device Skew Part-to-Part Skew (Diff) Minimum Input Swing Common Mode Range VPP < 500mV VPP 500mV tr/tf Output Rise/Fall Time 400 VEE +1.3 VEE +1.6 200 -0.4 -0.4 600 Min
1040 990 1100
0C Max
1240 1290 1400
25C Max
1260 1310 1430
70C Max
1280 1330 1470
Typ
1140 1140 1250
Min
1060 1010 1130
Typ
1160 1160 1280
Min
1080 1030 1170
Typ
1180 1180 1320
Min
1120 1070 1220
Typ
1220 1220 1370
Max
1320 1370 1520
Unit ps
Condition Note 1. Note 2.
tskew VPP VCMR
50 200 400 VEE +1.2 VEE +1.5 200
50 200 400 -0.4 -0.4 600 VEE +1.2 VEE +1.5 200
50 200 400 -0.4 -0.4 600 VEE +1.2 VEE +1.5 200
50 200
ps mV V
Note 3. Note 4. Note 5.
-0.4 -0.4 600 ps 20%-80%
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12) of the Motorola High Performance ECL Data Book (DL140/D). 2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12) of the Motorola High Performance ECL Data Book (DL140/D). 3. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the LVE222. A differential input as low as 50 mV will still produce full ECL levels at the output. 5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
PECL AC CHARACTERISTICS (VEE = GND; VCC = VCCO = VCC (min) to VCC (max))
-40C Symbol tPLH tPHL Characteristic Propagation Delay to Output IN (differential) IN (single-ended) MR Within-Device Skew Part-to-Part Skew (Diff) Minimum Input Swing Common Mode Range VPP < 500mV VPP 500mV tr/tf Output Rise/Fall Time 400 1.3 1.6 200 VCC -0.4 VCC -0.4 600 Min
1040 990 1100
0C Max
1240 1290 1400
25C Max
1260 1310 1430
70C Max
1280 1330 1470
Typ
1140 1140 1250
Min
1060 1010 1130
Typ
1160 1160 1280
Min
1080 1030 1170
Typ
1180 1180 1320
Min
1120 1070 1220
Typ
1220 1220 1370
Max
1320 1370 1520
Unit ps
Condition Note 1. Note 2.
tskew VPP VCMR
50 200 400 1.2 1.5 200
50 200 400 VCC -0.4 VCC -0.4 600 1.2 1.5 200
50 200 400 VCC -0.4 VCC -0.4 600 1.2 1.5 200
50 200
ps mV V
Note 3. Note 4. Note 5.
VCC -0.4 VCC -0.4 600 ps 20%-80%
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12) of the Motorola High Performance ECL Data Book (DL140/D). 2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 1-12) of the Motorola High Performance ECL Data Book (DL140/D). 3. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 4. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the LVE222. A differential input as low as 50 mV will still produce full ECL levels at the output. 5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min).
MOTOROLA
4-4
ECLinPS and ECLinPS Lite DL140 -- Rev 3
MC100LVE222
OUTLINE DIMENSIONS
FA SUFFIX TQFP PACKAGE CASE 848D-03 ISSUE C
4X
-X- X=L, M, N
4X TIPS
0.20 (0.008) H L-M N
0.20 (0.008) T L-M N
C L AB G
52 1
40 39
AB VIEW Y -M- B V
PLATING
3X VIEW
Y
-L-
F
BASE METAL
B1
13 14 26 27
J V1
0.13 (0.005)
A1 S1 A S
-N-
SECTION AB-AB
ROTATED 90_ CLOCKWISE
C -H- -T-
SEATING PLANE
4X
2 0.10 (0.004) T
4X
3 VIEW AA
NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION: MILLIMETER. 3 DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4 DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --- 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ --- 0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --- 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ --- 0_ 12 _ REF 5_ 13 _
0.05 (0.002)
S
W 1 C2
2XR
R1
0.25 (0.010)
GAGE PLANE
K C1 E Z VIEW AA
DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3
ECLinPS and ECLinPS Lite DL140 -- Rev 3
4-5
CCCC EEEE CCCC EEEE
M
U
D T L-M
S
N
S
MOTOROLA
MC100LVE222
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MOTOROLA 4-6
*MC100LVE222/D*
MC100LVE222/D ECLinPS and ECLinPS Lite DL140 -- Rev 3

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